ASIC Design and Verification training empowers the participants to contribute to ASIC (application-specific integrated circuit) industry. ASIC is designed for a specific application rather than going for general purpose designing. This designing supports the development of embedded systems.
The curriculum is designed to impart the knowledge and skills for RTL (Register Transfer Level) designing and netlist generation. Participants practice static time analysis (STA) for ASIC design verification and validating the timing performance of the design. The learning curve encompasses SOC designing and also focuses on HDL techniques for high performance designs intended for programmable logic devices.
Upon the completion of the raining you will be able to:
- Understand the fundamentals of logic designing and Analog/Mixed signal (AMS) IC designing
- Use Verilog, Linux, Tcl
- Develop advanced RTL design using Verilog
- Perform ASIC verification
- Conduct analysis of backend design parameter
- Conduct design Synthesis for ASIC methodologies
- Demonstrate high performance designs using HDL techniques
Target audience
- Final year students of electronics engineering courses
- Processionals from VLSI domain
- Professionals aspire to change their job profile from backend to front end
- Professionals willing to switch the domain
Prerequisites
Candidates having knowledge of digital design logic and system architecture are the ideal participants for this course.