CMOS & FPGA Design Flow Training lays emphasis on the designing, synthesis, implementation, and verification. The curriculum is designed to impart knowledge and skills on the use of tools and techniques used throughout the FPGA (Field-Programmable Gate Array) design cycle. Participants will learn RTL for designing; System Verilog and Xilinx for synthesis and implementation of HDL designs. For the verification purpose, the hands-on exposure on ModelSIM, QuestSIM, and Xilinx ISE is provided. The training collectively bestows to deliver a view point and approaches used in the industry for solving design problems.
Upon the completion of the training, you will be proficient in the following skills:
- Differentiate among different technologies say NMOS, PMOS, CMOS
- Understand the details of CMOS
- Design exercise using CMOS
- Fabrication flows and fundamentals
- Architectures of XILINX, ALTERA Devices
- Architecture based coding and constraints based synthesis
- Use industry standard tools
Target audience
- Final year students of electronics engineering courses
- Processionals from VLSI domain
- Professionals aspire to change their job profile from frontend to backend
- Professionals willing to switch the domain
Prerequisites
Candidates having knowledge of Register-Transfer Level (RTL) are the ideal participants for this course.